integrated device technology, inc. military and commercial temperature ranges may 1992 1992 integrated device technology, inc. 7.8 dsc-4610/3 fast cmos octal buffer/line driver idt54/74fct240/a/c idt54/74fct241/a/c idt54/74fct244/a/c idt54/74fct540/a/c idt54/74fct541/a/c features: idt54/74fct240/241/244/540/541 equivalent to fast tm speed and drive idt54/74fct240a/241a/244a/540a/541a 25% faster than fast idt54/74fct240c/241c/244c/540c/541c up to 55% faster than fast ? ol = 64ma (commercial) and 48ma (military) cmos power levels (1mw typ. static) product available in radiation tolerant and radiation enhanced versions military product compliant to mil-std-883, class b meets or exceeds jedec standard 18 specifications functional block diagrams 2529 cnv* 01?3 oe a da 0 ob 0 da 1 ob 1 da 2 ob 2 da 3 ob 3 oe b oa 0 db 0 oa 1 db 1 db 2 db 3 oa 2 oa 3 idt54/74fct240 oe a da 0 ob 0 da 1 ob 1 da 2 ob 2 da 3 ob 3 oe b * oa 0 db 0 oa 1 db 1 db 2 db 3 oa 2 oa 3 idt54/74fct241/244 *oe b for 241, oe b for 244 oe a d 0 oe b o 0 * d 1 d 2 d 3 d 4 d 5 d 6 d 7 o 1 * o 2 * o 3 * o 4 * o 5 * o 6 * o 7 * idt54/74fct540/541 *logic diagram shown for 'fct540. 'fct541 is the non-inverting option. 241 only description: the idt octal buffer/line drivers are built using an advanced dual metal cmos technology. the idt54/74fct240/a/c, idt54/74fct241/a/c and idt54/74fct244/a/c are designed to be employed as memory and address drivers, clock drivers and bus-oriented transmitter/receivers which provide improved board density. the idt54/74fct540/a/c and idt54/74fct541/a/c are similar in function to the idt54/74fct240/a/c and idt54/ 74fct244/a/c, respectively, except that the inputs and out- puts are on opposite sides of the package. this pinout arrangement makes these devices especially useful as output ports for microprocessors and as backplane drivers, allowing ease of layout and greater board density. 2606 dwg 01?3 1 the idt logo is a registered trademark of integrated device technology, inc. fast is a trademark of national semiconductor co.
idt54/74fct240/241/244/540/541/a/c fast cmos octal buffer/line driver military and commercial temperature ranges 7.8 2 pin configurations idt54/74fct240 2529 cnv* 04?9 2606 cnv* 04?9 idt54/74fct241/244 idt54/74fct540/541 *oe b for 241, oe b for 244 * o x for 540, o x for 541 oe a da 0 ob 0 da 1 ob 1 da 2 ob 2 da 3 ob 3 gnd oe b * oa 0 db 0 oa 1 db 1 db 2 db 3 oa 2 oa 3 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dip/soic/cerpack top view p20-1 d20-1 so20-2 & e20-1 index da 1 ob 1 da 2 ob 2 da 3 oa 0 db 0 oa 1 db 1 oa 2 da 0 ob 0 oe a v cc oe b * ob 3 gnd db 3 oa 3 db 2 lcc top view 3 2 20 19 1 4 5 6 7 8 18 17 16 15 14 9 10111213 l20-2 oe a da 0 ob 0 da 1 ob 1 da 2 ob 2 da 3 ob 3 gnd oe b oa 0 db 0 oa 1 db 1 db 2 db 3 oa 2 oa 3 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dip/soic/cerpack top view p20-1 d20-1 so20-2 & e20-1 index da 1 ob 1 da 2 ob 2 da 3 oa 0 db 0 oa 1 db 1 oa 2 da 0 ob 0 oe a v cc oe b ob 3 gnd db 3 oa 3 db 2 lcc top view 3 2 20 19 1 4 5 6 7 8 18 17 16 15 14 9 10111213 l20-2 oe a d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gnd oe b o 0 * o 1 * o 2 * o 3 * o 5 * o 7 * o 4 * o 6 * v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dip/soic/cerpack top view p20-1 d20-1 so20-2 & e20-1 index d 2 o 0 * d 0 d 1 oe a v cc oe b gnd lcc top view o 1 * o 2 * o 3 * o 4 * d 3 d 4 d 5 d 6 o 7 * o 6 * o 5 * d 7 3 2 20 19 1 4 5 6 7 8 18 17 16 15 14 9 10111213 l20-2
idt54/74fct240/241/244/540/541/a/c fast cmos octal buffer/line driver military and commercial temperature ranges 7.8 3 pin description function table note: 2606 tbl 04 1. oe b for 241 only. notes: 2606 tbl 05 1. h = high voltage level x = dont care l = low voltage level z = high impedance 2. oe b for 241 only. absolute maximum ratings (1) capacitance (t a = +25 c, f = 1.0mhz) notes: 2606 tbl 01 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed v cc by +0.5v unless otherwise noted. 2. input and v cc terminals only. 3. outputs and i/o terminals only. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf note: 2606 tbl 02 1. this parameter is measured at characterization but not tested. symbol rating commercial military unit v term (2) terminal voltage with respect to gnd C0.5 to +7.0 C0.5 to +7.0 v v term (3) terminal voltage with respect to gnd C0.5 to v cc C0.5 to v cc v t a operating temperature 0 to +70 C55 to +125 c t bias temperature under bias C55 to +125 C65 to +135 c t stg storage temperature C55 to +125 C65 to +150 c p t power dissipation 0.5 0.5 w i out dc output current 120 120 ma pin names description oe a , oe b 3Cstate output enable inputs (active low) oe b (1) 3Cstate output enable input (active high) dxx inputs oxx outputs inputs (1) outputs (1) oe oe a oe oe b oe b (2) d 240 241 244 540 541 llhlhl lhl llhhlhhlh hhl xzzzzz
idt54/74fct240/241/244/540/541/a/c fast cmos octal buffer/line driver military and commercial temperature ranges 7.8 4 dc electrical characteristics over operating range following conditions apply unless otherwise specified: v lc = 0.2v; v hc = v cc C 0.2v commercial: t a = 0 c to +70 c, v cc = 5.0v 5%; military: t a = C55 c to +125 c, v cc = 5.0v 10% notes: 2606 tbl 03 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the short circuit test should not exceed one second. 4. this parameter is guaranteed but not tested. symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2.0 v v il input low level guaranteed logic low level 0.8 v i i h input high current v cc = max. v i = v cc 5 m a v i = 2.7v 5 (4) i i l input low current v i = 0.5v C5 (4) v i = gnd C5 i ozh off state (high impedance) v cc = max. v o = v cc 10 m a output current v o = 2.7v 10 (4) i ozl v o = 0.5v C10 (4) v o = gnd C10 v ik clamp diode voltage v cc = min., i n = C18ma C0.7 C1.2 v i os short circuit current v cc = max. (3) , v o = gnd C60 C120 ma v oh output high voltage v cc = 3v, v in = v lc or v hc , i oh = C32 m av hc v cc v v cc = min. i oh = C300 m av hc v cc v in = v ih or v il i oh = C12ma mil. 2.4 4.3 i oh = C15ma com'l. 2.4 4.3 v ol output low voltage v cc = 3v, v in = v lc or v hc , i ol = 300 m a gnd v lc v v cc = min. i ol = 300 m a gnd v lc (4) v in = v ih or v il i ol = 48ma mil. 0.3 0.55 i ol = 64ma com'l. 0.3 0.55
idt54/74fct240/241/244/540/541/a/c fast cmos octal buffer/line driver military and commercial temperature ranges 7.8 5 power supply characteristics v lc = 0.2v; v hc = v cc C 0.2v notes: 2606 tbl 06 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz. symbol parameter test conditions (1) min. typ. (2) max. unit i cc quiescent power supply current v cc = max. v in 3 v hc ; v in v lc 0.2 1.5 ma d i cc quiescent power supply current ttl inputs high v cc = max. v in = 3.4v (3) 0.5 2.0 ma i ccd dynamic power supply current (4) v cc = max. outputs open oe a = oe b = gnd or oe a = gnd, oe b = v cc one input toggling 50% duty cycle v in 3 v hc v in v lc 0.15 0.25 ma/ mhz i c total power supply current (6) v cc = max. outputs open fi = 10mhz 50% duty cycle v in 3 v hc v in v lc (fct) 1.7 4.0 ma oe a = oe b = gnd or oe a = gnd, oe b = v cc one bit toggling v in = 3.4v v in = gnd 2.0 5.0 v cc = max. outputs open fi = 5mhz 50% duty cycle v in 3 v hc v in v lc (fct) 3.2 6.5 (5) oe a = oe b = gnd or oe a = gnd, oe b = v cc eight bits toggling v in = 3.4v v in = gnd 5.2 14.5 (5)
idt54/74fct240/241/244/540/541/a/c fast cmos octal buffer/line driver military and commercial temperature ranges 7.8 6 switching characteristics over operating range for fct240 (1,2) 2606 tbl 07 switching characteristics over operating range for fct241 and fct244(1,2) switching characteristics over operating range for fct241 and fct244 (1,2) 54/74fct241/244 54/74fct241a/244a 54/74fct241c/244c com'l. mil. com'l. mil. com'l. mil. symbol parameter condition min. max. min. max. min. max. min. max. min. max. min. max. unit t plh t phl propagation delay d n to o n c l = 50pf r l = 500 w 1.5 6.5 1.5 7.0 1.5 4.8 1.5 5.1 1.5 4.1 1.5 4.6 ns t pzh t pzl output enable time 1.5 8.0 1.5 8.5 1.5 6.2 1.5 6.5 1.5 5.8 1.5 6.5 ns t phz t plz output disable time 1.5 7.0 1.5 7.5 1.5 5.6 1.5 5.9 1.5 5.2 1.5 5.7 ns 2606 tbl 08 switching characteristics over operating range for fct540 and fct541 (1,2) notes: 2606 tbl 09 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 54/74fct240 54/74fct240a 54/74fct240c com'l. mil. com'l. mil. com'l. mil. symbol parameter condition min. max. min. max. min. max. min. max. min. max. min. max. unit t plh t phl propagation delay d n to o n c l = 50pf r l = 500 w 1.5 8.0 1.5 9.0 1.5 4.8 1.5 5.1 1.5 4.3 1.5 4.7 ns t pzh t pzl output enable time 1.5 10.0 1.5 10.5 1.5 6.2 1.5 6.5 1.5 5.8 1.5 6.5 ns t phz t plz output disable time 1.5 9.5 1.5 10.0 1.5 5.6 1.5 5.9 1.5 5.2 1.5 5.7 ns 54/74fct540/541 54/74fct540a/541a 54/74fct540c/541c com'l. mil. com'l. mil. com'l. mil. symbol parameter condition min. max. min. max. min. max. min. max. min. max. min. max. unit t plh t phl propagation delay d n to o n idt54/74fct540 c l = 50pf r l = 500 w 1.5 8.5 1.5 9.5 1.5 4.8 1.5 5.1 1.5 4.3 1.5 4.7 ns t plh t phl propagation delay d n to o n idt54/74fct541 1.5 8.0 1.5 9.0 1.5 4.8 1.5 5.1 1.5 4.1 1.5 4.6 ns t pzh t pzl output enable time 1.5 10.0 1.5 10.5 1.5 6.2 1.5 6.5 1.5 5.8 1.5 6.5 ns t phz t plz output disable time 1.5 9.5 1.5 10.0 1.5 5.6 1.5 5.9 1.5 5.2 1.5 5.7 ns
idt54/74fct240/241/244/540/541/a/c fast cmos octal buffer/line driver military and commercial temperature ranges 7.8 7 test circuits and waveforms test circuits for all outputs enable and disable times propagation delay set-up, hold and release times pulse width pulse generator data input timing input asynchronous control preset clear etc. synchronous control preset clear clock enable etc. 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v t su t h t rem h t su r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v same phase input transition 3v 1.5v 0v 1.5v v oh v ol t plh t phl output opposite phase input transition control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol v oh 3v 1.5v 0v t plh t phl 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable high-low-high pulse low-high-low pulse t w 1.5v 1.5v t notes 2606 drw 10 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0 mhz; z o 50 w ; t f 2.5ns; t r 2.5ns. switch position test switch open drain disable low closed enable low all other tests open definitions: 2606 tbl 10 c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
idt54/74fct240/241/244/540/541/a/c fast cmos octal buffer/line driver military and commercial temperature ranges 7.8 8 ordering information 2606 cnv* 15 idt xx temp. range xxxx device type x package x process blank b p d so l e 240 241 244 540 541 240a 241a 244a 540a 541a 240c 241c 244c 540c 541c commercial mil-std-883, class b plastic dip cerdip small outline ic leadless chip carrier cerpack inverting octal buffer/line driver non-inverting octal buffer/line driver non-inverting octal buffer/line driver inverting octal buffer/line driver non-inverting octal buffer/line driver fast inverting octal buffer/line driver fast non-inverting octal buffer/line driver fast non-inverting octal buffer/line driver fast inverting octal buffer/line driver fast non-inverting octal buffer/line driver super fast inverting octal buffer/line driver super fast non-inverting octal buffer/line driver super fast non-inverting octal buffer/line driver super fast inverting octal buffer/line driver super fast non-inverting octal buffer/line driver 54 74 C55 c to +125 c 0 c to +70 c fct
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